Satadru Nath Sarkar
15+ years of successful CMOS Design and Technology development experience in all three different segments (Foundry/Fabless/IDM) of Semiconductor... | San Diego, California, United States
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Satadru Nath Sarkar’s Emails sa****@qu****.com
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Satadru Nath Sarkar’s Location San Diego, California, United States
Satadru Nath Sarkar’s Expertise 15+ years of successful CMOS Design and Technology development experience in all three different segments (Foundry/Fabless/IDM) of Semiconductor Industry. As a CMOS Design - Technology co-optimization professional in different leading Semiconductor companies, I have very broader experience in the bottom up development flows in the following areas. • CMOS Device design and SPICE modelling from 90nm node to 3nm node. • PDK development and process test chip design across various technology nodes. • Standard cell circuit design and Timing characterization from 14nm to 3nm node. • Design-Technology Co-optimization and PPA analysis
Satadru Nath Sarkar’s Current Industry Nvidia
Satadru
Nath Sarkar’s Prior Industry
Semiconductor Laboratory Department Of Space
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Infineon Technologies
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Ibm
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Globalfoundries
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Intel
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Qualcomm
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Imec
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Nvidia
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Work Experience
Nvidia
Principal Engineer
Sun Oct 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Qualcomm
Senior Staff Engineer
Sun Mar 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Oct 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)
Imec
R&D Engineer
Wed Aug 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Mar 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Qualcomm
Engineer, Senior Staff/Manager
Sun May 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jul 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Component Design Engineer
Thu Aug 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Apr 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Globalfoundries
MTS
Fri Apr 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jul 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Globalfoundries
Principal Engineer
Fri Jan 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Apr 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Ibm
ISDA Partner from Chartered Semiconductor
Mon Aug 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Feb 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
Infineon Technologies
Design Engineer
Sat May 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Aug 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time)
Semiconductor Laboratory Department Of Space
Engineer
Thu Mar 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat May 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)Skills
Languages
Satadru Nath Sarkar Email Addresses
FAQ About Satadru Nath Sarkar
-
Satadru Nath Sarkar is located at
San Diego, California, United States -
Satadru Nath Sarkar is a
15+ years of successful CMOS Design and Technology development experience in all three different segments (Foundry/Fabless/IDM) of Semiconductor Industry. As a CMOS Design - Technology co-optimization professional in different leading Semiconductor companies, I have very broader experience in the bottom up development flows in the following areas. • CMOS Device design and SPICE modelling from 90nm node to 3nm node. • PDK development and process test chip design across various technology nodes. • Standard cell circuit design and Timing characterization from 14nm to 3nm node. • Design-Technology Co-optimization and PPA analysis Nvidia -
Satadru Nath Sarkar currently works in the
Nvidia -
Satadru Nath Sarkar specializes in
15+ years of successful CMOS Design and Technology development experience in all three different segments (Foundry/Fabless/IDM) of Semiconductor Industry. As a CMOS Design - Technology co-optimization professional in different leading Semiconductor companies, I have very broader experience in the bottom up development flows in the following areas. • CMOS Device design and SPICE modelling from 90nm node to 3nm node. • PDK development and process test chip design across various technology nodes. • Standard cell circuit design and Timing characterization from 14nm to 3nm node. • Design-Technology Co-optimization and PPA analysis -
Satadru Nath Sarkar speaks the following languages:
No languages available. -
Satadru Nath Sarkar has prior experience in the following industries:
Qualcomm , Imec , Qualcomm , Intel , Globalfoundries , Globalfoundries , Ibm , Infineon Technologies , Semiconductor Laboratory Department Of Space -
Satadru Nath Sarkar has the following professional experience:
Nvidia , Qualcomm , Imec , Qualcomm , Intel , Globalfoundries , Globalfoundries , Ibm , Infineon Technologies , Semiconductor Laboratory Department Of Space . -
You can view Satadru Nath Sarkar’s
LinkedIn profile at LinkedIn URL. -
Satadru Nath Sarkar’s work email addresses are
[email protected] . -
Satadru Nath Sarkar works at
Nvidia
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